Draw the circuit of 2's complement binary adder-subtractor and using it explain the addition of binary equivalent of decimal number 9 and binary equivalent of decimal number 4 .
A 2's complement binary adder-subtractor circuit is designed to perform both addition and subtraction of binary numbers using a single adder circuit. The circuit consists of a binary adder, usually a full-adder chain, and an XOR gate connected to each bit of the second operand (B). A control input, often labeled as SUB or M, determines the operation: ________ ____ ___ __________ ___.
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Refer to Fig. 15.4 in your study material showing the geometry of the electron beam deflection in a CRT. In this CRT the length of deflection plates (L) is and the distance between screen and centre of the deflection plates (R) is
. Accelerating voltage applied to the anode is 1200 V and applied deflection voltage is 80 V. If the deflection suffered by the electron beam at the edge of the deflection plate (h) is 1 mm, calculate the plate separation (s). Determine the deflection observed on the CRT screen (y) and calculate the deflection sensitivity.
Design and draw shunt voltage regulator using a zener diode to provide output with maximum load current of
. Assume that the input unregulated dc voltage is
and the minimum zener current is
.
Obtain the expression for the output of the following logic circuit. Write its truth table. Which gate is represented by this circuit?
Design and draw a circuit using an op-amp to get at output for input less than
and
at output for input greater than
.
Draw the structure of an n-channel JFET with appropriate voltage bias and explain the process of pinch-off. Explain the various regions on the drain characteristic of this JFET for VDS > 0 and .
Using the Boolean laws and theorems prove the following identities:
i.
ii.
iii.
iv.
v.
and
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